In a metal S/D (Source/Drain) MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has been reported, the source/drain, and its extension portion are formed of a metal semiconductor compound such as silicide. However, an overlap length of the extension portions and gate electrode which determines a current drivability and a short channel effect of the metal S/D MISFET are not positively controlled in spite of their importance. Particularly, this control is very important in case of a scaled down MISFET having a gate length equal to or less than 30 nm.
In case of a metal S/D MISFET in which the extension portion is formed with a silicide layer, the film thickness and horizontal direction growth of the silicide layer at the gate edge needs to be accurately controlled to control the overlap length.
Meanwhile, when a nickel silicide layer is taken as an example, to control the film thickness of the nickel silicide layer, an initially deposited nickel film thickness and the temperature and time of heat processing upon formation of nickel silicide are controlled. However, it is difficult to sufficiently control diffusion of nickel due to influences such as variation of the deposition amount of the nickel film and variation of the temperature upon reaction.
Particularly, in case the volume of silicon to be converted into silicide is relatively less than metal to be reacted like a 3-dimensional structure device including a MISFET on an ultrathin SOI (Silicon On Insulator), MISFET having a narrow gate width, FinFET or Nano-wire MISFET, conversion of a narrow portion of silicon into nickel silicide is accelerated, and the narrow portion is abnormally grown. When this abnormal growth occurs, conversion into silicide in a channel direction is accelerated, and therefore it becomes more difficult to control the overlap length.
Further, with a device which uses a SOI substrate, the abnormal growth and agglomeration of silicide due to the heat gradient caused by a small thermal conductivity of a BOX (Buried OXide) layer locally occur, and therefore it becomes still more difficult to control the gate overlap length.